The present invention generally relates to differential digital circuits and the timing behavior thereof.
Digital circuits are normally operated in a two-level, or binary, mode. This means that at a steady state, each input and output is in one of two conditions. These conditions (or states) are often referred to as true or false states, high (V.sub.h) or low (V.sub.l) levels, or `1` or `0` states, respectively. Because circuit outputs are generally voltages, these two states are characterized by two voltage ranges based on a higher voltage V.sub.ih and a lower voltage V.sub.il, where V.sub.ih &gt;V.sub.il. The voltages V.sub.ih and V.sub.il are also called the high and low logic thresholds. It is agreed that--as shown in FIG. 1--if a nodal voltage V satisfies the inequality V&gt;V.sub.ih, then the node is in a high state, and if V&lt;V.sub.il, the node is in a low state.
For some applications, the two-level mode has been proved insufficient, and instead thereof, a differential logic is applied. In digital circuits using the differential logic (also referred hereafter as differential digital circuits, or simply differential circuits), the signal voltage is defined as the difference between two node voltages V=V.sub.p -V.sub.n. For the logic state of V, the conditions as described for the two-level mode apply. In a steady state, the two node voltages V.sub.p and V.sub.n of the differential logic always have opposite states, i.e. if V.sub.p &gt;V.sub.ih then V.sub.n &lt;V.sub.il, and vice versa. Among other advantages, circuits applying differential logic generally exhibit constant power supply current, a comparably low voltage swing and thus high speed, low susceptibility to noise and comparably low noise generation.
Differential circuits, including the differential digital circuits, have formerly been implemented in bipolar technologies such as in ECL (emitter-coupled logic) circuits. ECL is often used in computers that require high speed. To achieve such high speeds, ECL consumes a large amount of electric power, requiring expensive cooling. Current trends in the electronic industry towards higher integration and smaller systems also force an application of differential circuits in MOS (metal oxide semiconductor) technologies. The main differences between bipolar and MOS transistors, used to implement differential circuits, are the following. A single IC chip cannot be packed with as many transistors in ECL as in MOS. If too many transistors are placed on an ECL chip, it becomes damaged by the excessive heat. MOS chips consume very little power if the signals do not change with a very high frequency; therefore, a large number of transistors can be packed onto a single chip. Further more, MOS transistors show higher threshold voltages and a lower transconductance at comparable speed and power supply currents.
FIG. 2 shows an inverter circuit as an example for a differential digital circuit. A current source 10 feeds a first current path 20 and a second current path 30. The first current path 20 comprises a first current switch 40 and a first load 50, and the second current path 30 comprises a second current switch 60 and a second load 70. The first 40 and second 60 current switches are normally embodied by transistor elements, such as bipolar or MOS transistors, and receive at their control electrodes differential input signals IN.sub.p and IN.sub.n, respectively. The first 50 and second 70 load may also be embodied by transistor elements, such as MOS transistors, or by other resistor means as known in the art. Each one of the current paths 20 and 30 respectively provides a differential output signal OUT.sub.p or OUT.sub.n at a node between the current switches and the load.
In operation, the higher signal of the differential input signals IN.sub.p and IN.sub.n switches on the respective one of the current switches 40 or 60, so that the potential of the output signal (OUT.sub.p or OUT.sub.n) in that current path will be drawn from a higher to a lower potential. Accordingly, the lower signal of the differential signals IN.sub.p and IN.sub.n switches off the other one of the current switches 40 or 60, so that the potential of the output signal in that current path will be drawn from a lower to a higher potential. The circuit of FIG. 2 thus inverts the differential input signals IN.sub.p and IN.sub.n.
It is clear that the function of the circuit in FIG. 2 can be modified by exchanging the input signals or the output signals resulting in a non-inverting buffer.
In general, a state transition is a change of a node voltage from a first state to a second state, where in a digital circuit the state transition normally is between two defined states. FIG. 3 shows an example for such a state transition. The time while a voltage is in a range between the threshold voltages V.sub.ih and V.sub.il is called the transition time t.sub.tr. For physical reasons the transition time must be non zero, t.sub.tr &gt;0.
The point in time when a voltage reaches V=(V.sub.ih +V.sub.il)/2 is generally referred to as a timing mark of the transition. For differential signals, the timing mark is the point in time, when the differential signals are equal. In FIG. 3, the transition starts at a time t.sub.1 and ends at a time t.sub.3, whereby at a time t.sub.2 the two differential signals are equal and reach the voltage (V.sub.ih +V.sub.il)/2. The transition time is defined as t.sub.tr =t.sub.3 -t.sub.1. The transition mark of that transition is at t.sub.2.
Timing information is transmitted or processed when signals change from one state to another and generally comprises information about timing marks. A digital circuit, which is processing or transmitting timing information, generates a sequence of output state transitions as a result of a sequence of input state transitions. Output state transitions occur at times t.sub.o (1), t.sub.o (2) . . . t.sub.o (N) caused by input state transitions that occur at times t.sub.i (1), t.sub.i (2) . . . t.sub.i (N), as depicted in FIG. 4a.
The relationship between timing information of input transitions must be reflected at the output of the system. Further more, the time elapsing between input state changes should also elapse between output state changes caused by their respective input state changes. Otherwise the system has changed the timing information which should be avoided in most applications. Thus, a digital circuit generates accurate timing, if the following equation for the transition times is satisfied: EQU t.sub.o (k+1)-t.sub.o (k)=t.sub.i (k+1)-t.sub.i (k), where k is an integer.(eq.1)
The time difference between a timing mark t.sub.i (k) of a transition at an input of a system or device, and a timing mark t.sub.o (k) of a thereto corresponding output transition is called the propagation delay t.sub.pd (k), with t.sub.pd (k)=t.sub.o (k)-t.sub.i (k). For an ideal digital circuit, the propagation delay is a constant value with t.sub.pd (k)=t.sub.pd (k+n) where n is an integer. However, in real digital circuits the propagation delay t.sub.pd (k) might differ depending on the actual input state, the frequency of state changes at the input, and so forth.
In particular when digital electronic circuits are used for time measuring, e.g. in testing applications for testing e.g. integrated circuits (IC's) or other electronic devices, it is crucial for the operation that the circuits provide an accurate timing, i.e., the variation of the propagation delay t.sub.pd (k) should be small with respect to the transition time of the signal to be measured, transmitted or otherwise processed.
The propagation delay t.sub.pd (k) of a differential circuit is commonly defined as the time elapsing between corresponding time marks, i.e the point in time when V.sub.i =0 or V.sub.ip =V.sub.in and the point in time when V.sub.o =0 or V.sub.op =V.sub.on, as depicted in FIG. 4b. This is in accordance with the time elapsing between the transition timings as described above.
Miniaturization of electrical circuits is generally envisaged since miniaturization means not only that a higher integration of the circuits can be achieved, but also that higher frequencies can be applied due to the smaller feature sizes. However, with an increased integration and miniaturization of differential circuits, it has been found that the timing behavior, such as the propagation delay t.sub.pd (k), significantly starts to vary, even between identical differential circuits. Further more, it was detected that e.g. the propagation delay t.sub.pd (k) turns out to diverge and not to be a constant value for a specific circuit, so that the timing information will be changed by that circuit. This leads to timing defects which are completely unacceptable for most applications, and in particular, for timing sensitive applications such as in testing applications.
Specifically since differential circuits are mainly used for high precision applications, the effect of an unpredictable timing behavior has been found as an enormous drawback for that technology. However, a reason for that variation in timing behavior could not have been sufficiently given in the art, so that the circuit designers had to either accept only a certain degree of integration and miniaturization, or to use different technologies.